ASIC Design Engineers to our R&D site in Stockholm

StockholmCompetitive0 applicants

About this role

Do you want to work with advanced ASIC development in the forefront of technology? Are you ready to join a team responsible for the very heart of the Axis products - the ARTPEC SoC chip - where your contribution really matters and where team collaboration is the way to success? We are now looking for ASIC Design Engineers to further strengthen the AXIS ASIC development in Stockholm.

Your Future Team

The AXIS ASIC Department is at the heart of our technology, developing our own ASICs with hardware acceleration for essential functions in surveillance cameras. We design, develop, implement, integrate, and verify hardware modules that give us the competitive edge. Our team is a mix of junior and senior members, all highly skilled and motivated. We believe in an open working environment and strong, collaborative teamwork.

Learn more; https://newsroom.axis.com/article/artpec-foundation-quality

Who are we looking for/Who are you?

You are curious and have a great passion for technology. You love challenges and enjoy solving them in a team-focused atmosphere. We also believe that you are analytical and enjoy sharing your knowledge and ideas with both senior and junior team members.

A suitable background would be a bachelor's or master's degree in electrical engineering, computer science, engineering physics or similar.

Technical Expertise

Proven expertise as a skilled engineer with a passion for advanced ASIC development and experience in digital ASIC design.

Proficiency in HDLs (SystemVerilog), scripting languages (e.g., Python/TCL), and EDA tools (e.g., Synopsys/Cadence/Siemens EDA).

Strong understanding of digital logic design principles, microarchitecture, and computer architecture.

Experience with ASIC design flows.

Familiarity with low-power design techniques, clock/reset domain crossing, and synchronization methods.

Experience with integrate IP blocks into a robust system architecture.

Experience with 3rd party IPs, e.g. ARM, Synopsys and Cadence.

Good commun

EU Requirements

Job Details

Posted5 September 2026
Closes5 October 2026

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