ASIC Verification Engineer (PCIe)

About this role

Responsibilities

• Define and execute detailed verification strategies for ASIC/SoC components, with a strong focus on PCIe IP and associated subsystems
• Develop, optimize, and maintain verification environments using SystemVerilog and UVM methodologies
• Create reusable testbenches, verification components, and structured test cases
• Perform functional validation, regression testing, and coverage-driven verification to ensure design quality
• Analyze and debug issues across RTL, gate-level, and system-level implementations
• Collaborate closely with design, architecture, and firmware teams to resolve technical challenges
• Ensure compliance with PCIe standards (Gen3/Gen4/Gen5 or higher) through systematic validation
• Integrate and utilize Verification IP (VIP) for PCIe and other supported protocols
• Track verification progress, monitor coverage metrics, and provide regular status updates
• Educational Qualification
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• Required Skills & Experience
• Strong background in ASIC/SoC verification
• Proficiency in SystemVerilog and UVM-based verification techniques
• Hands-on experience with PCIe protocol verification
• Solid understanding of digital design concepts including RTL, FSMs, timing analysis, and clock domain crossing
• Experience with simulation tools such as VCS, Questa, or Xcelium
• Expertise in debugging techniques and waveform analysis
• Preferred Skills
• Experience with PCIe LTSSM, link training, and transaction layer debugging
• Knowledge of high-speed interfaces such as Ethernet, USB, or DDR
• Exposure to formal verification or emu